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[MultiHighlight]
Syntax=
File=

[Comment]
1=***************************************************************************
2=
3=<b>Syntax:          VHDL                                              </b>
4=<b>Version:         0.0                                               </b>
5=<b>Date:            31.03.2008                                        </b>
6=<b>Author:          n.n. from Ultraedit - see example for success     </b>
7=
8=<b>source file:     VHDL.txt                                          </b>
9=<b>filter:          ultraedit2rjedit-awk.txt                          </b>
10=<b>filter version:  $Revision: 1.23 $/$Date: 2006/08/15 20:05:10 $    </b>
11=
12=<b>file extensions: VHD VHO VHDL                                      </b>
13=
14=***************************************************************************

[Sample]
1=LIBRARY IEEE;
2=USE IEEE.std_logic_1164.ALL;
3=
4=ENTITY YCbCr422ToRGB IS
5=  GENERIC (
6=    usePipe   : boolean := FALSE;
7=    colorBits : integer := 8
8=  );
9=  PORT (
10=    clk             : IN  std_logic
11=  );
12=END ENTITY


